C508_01 Datasheet, PDF (26/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Memory Organization
3.1
Program Memory, “Code Space”
The C508-4R has 32 Kbytes of Read-Only program Memory (ROM), while the C508-4E
provides 32 Kbytes of OTP program memory. The program memory can be externally
expanded up to 64 Kbytes. If the EA pin is held high, the C508-4R executes program
code out of the internal ROM unless the program counter address exceeds 7FFF_H.
Address locations 8000_H through FFFF_H are then fetched from the external program
memory. If the EA pin is held low, the C508 fetches all instructions from the external
program memory.
3.2
Data Memory, “Data Space”
The data memory address space consists of an internal and an external memory space.
The internal data memory is divided into three physically separate and distinct blocks:
the lower 128 bytes of RAM, the upper 128 bytes of RAM, and the 128-byte Special
Function Register (SFR).
While the upper 128 bytes of data memory and the SFR area share the same address
locations, they are accessed through different addressing modes. The lower 128 bytes
of data memory can be accessed through direct or register indirect addressing; the upper
128 bytes of RAM can be accessed through register indirect addressing; the special
function registers are accessible through direct addressing. Four 8-register banks, each
bank consisting of eight 8-bit general-purpose registers, occupy locations 0 through 1F_H
in the lower RAM area. The next 16 bytes, locations 20_H through 2F_H, contain 128
directly addressable bit locations. The stack can be located anywhere in the internal
RAM area, and the stack depth can be expanded up to 256 bytes.
The external data memory can be expanded up to 64 Kbytes and can be accessed by
instructions that use a 16-bit or an 8-bit address. The internal XRAM is located in the
external address memory area at addresses FC00_H to FFFF_H. Using MOVX instruction
with addresses pointing to this address area, allows access to either internal XRAM or
external data RAM.
3.3
General Purpose Registers
The lower 32 locations of the internal RAM are assigned to four banks of eight General
Purpose Registers (GPRs) each. Only one of these banks may be enabled at a time.
Two bits in the Program Status Word, RS0 (PSW.3) and RS1 (PSW.4), select the active
register bank (see description of the PSW in Chapter 2). This allows fast context
switching, which is useful when entering subroutines or interrupt service routines.
The eight general purpose registers of the selected register bank may be accessed by
register addressing. With register addressing, the instruction op code indicates which
register is to be used. For indirect addressing, R0 and R1 are used as pointers or index
registers to address internal or external memory (for example: MOV @R0).
User’s Manual
3-2
2001-05