C508_01 Datasheet, PDF (146/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Bit
CT2RES
CT2R
CLK2
CLK1
CLK0
Function
Compare Timer 2 reset control
Compare Timer 2 run/stop control
These two bits controls the start, stop, and reset function of the
Compare Timer 2. CT2RES is used to reset Compare Timer 2; and
CT2R is used to start or stop Compare Timer 2. The following table
shows the functions of these two bits:
CT2RES CT2R Function
0
0
Compare Timer 2 is stopped; compare output
COUT3 stays in the logic state as it is.
0
1
Compare Timer 2 is running. If CT2R is set the
first time after reset, COUT3 is set to the logic
state as defined by bit COUT3I of SFR COINI.
1
0
Compare Timer 2 is stopped and reset. The
output COUT3 is set to the logic state as defined
by bit COUT3I of SFR COINI (default after reset).
1
1
Compare Timer 2 is further running.
ECT2O must be set for COUT3 signal output enable.
Compare Timer 2 input clock selection
The input clock for the Compare Timer 2 is derived from the clock rate
f_OSC of the C508 via a programmable prescaler. The following table
shows the programmable prescaler ratios.
CLK2
0
0
0
0
1
1
1
1
CLK1
0
0
1
1
0
0
1
1
CLK0
0
1
0
1
0
1
0
1
Function
Compare Timer 2 input clock is 2 f_OSC
Compare Timer 2 input clock is f_OSC
Compare Timer 2 input clock is f_OSC/2
Compare Timer 2 input clock is f_OSC/4
Compare Timer 2 input clock is f_OSC/8
Compare Timer 2 input clock is f_OSC/16
Compare Timer 2 input clock is f_OSC/32
Compare Timer 2 input clock is f_OSC/64
Note: With a reset operation (external or internal) Compare Timer 2 is reset (000_H) and
stopped. When software power-down mode is entered with CT2RES bit of SFR
CT2CON set, the Compare Timer 2 is reset after the execution of a wake-up from
User’s Manual
6-81
2001-05