C508_01 Datasheet, PDF (108/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.2.2.5 Capture Function
Each of the Compare/Capture registers T2CC1 to T2CC3 and the CRC register can be
used to latch the current 16-bit value of the Timer 2 registers TL2 and TH2. Two different
modes are provided for this function. In mode 0, an external event latches the Timer 2
contents to a dedicated capture register. In mode 1, a capture will occur upon writing to
the low order byte of the dedicated 16-bit capture register. This mode allows the software
to read the contents of Timer 2 “on-the-fly”.
In mode 0, the external event causing a capture is:
– For T2CC registers 1 to 3: a positive transition at pins T2CC1 to T2CC3 of Port 5
– For the CRC register: a positive or negative transition at the corresponding pin,
depending on the status of the bit I3FR in SFR T2CON. lf the edge flag is cleared,
a capture occurs in response to a negative transition. lf the edge flag is set, a
capture occurs in response to a positive transition at pin P5.0 / T2CC0 / INT3.
In both cases, the appropriate Port 5 pin is used as input and the port latch must be
programmed to contain a one (1). The external input is sampled in every machine cycle.
When the sampled input shows a low (high) level in one cycle and a high (low) in the next
cycle, a transition is recognized. The Timer 2 contents are latched to the appropriate
capture register in the cycle following the one in which the transition was identified.
In mode 0: a transition at the external capture inputs of registers T2CC1 to T2CC3 will
also set the corresponding external interrupt request flags IEX4 to IEX6. lf the interrupts
are enabled, an external capture signal will cause the CPU to vector to the appropriate
interrupt service routine.
In mode 1: a capture occurs in response to a write instruction to the low order byte of a
capture register. The write-to-register signal (example, write-to-CRCL) is used to initiate
a capture. The value written to the dedicated capture register is irrelevant for this
function. The Timer 2 contents will be latched into the appropriate capture register in the
cycle following the write instruction. In this mode no interrupt request will be generated.
Figure 6-21 illustrates the operation of the CRC register, while Figure 6-22 shows the
operation of the Compare/Capture registers 1 to 3.
The two capture modes can be established individually for each capture register by bits
in SFR CCEN (Compare/Capture enable register). That means, in contrast to the
compare modes, it is possible to simultaneously select mode 0 for one capture register
and mode 1 for another register.
User’s Manual
6-43
2001-05