C508_01 Datasheet, PDF (237/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Power Saving Modes
9
Power Saving Modes
The C508 provides two basic power saving modes: the idle mode and the power-down
mode. Additionally, a slow down mode is available. This power saving mode reduces the
internal clock rate in normal operating mode and it can also be used for further power
reduction in idle mode.
9.1
Power Saving Mode Control Registers
The functions of the power saving modes are controlled by bits located in the Special
Function Registers PCON and PCON1. The SFR PCON is located at SFR address 87_H.
PCON1 is located in the mapped SFR area (RMAP = 1) at SFR address 88_H. Bit RMAP,
which controls the access to the mapped SFR area, is located in SFR SYSCON (B1_H).
Bits PDE and PDS selects the power-down mode; while bits IDLE and IDLS selects the
idle mode. These bits are all located in SFR PCON. If the power-down mode and the idle
mode are set at the same time, power down mode takes precedence. Furthermore,
register PCON contains two general purpose flags. For example, the flag bits GF0 and
GF1 can be used to give an indication if an interrupt occurred during normal operation
or during idle mode. For this, an instruction that activates idle mode can also set one or
both flag bits. When idle mode is terminated by an interrupt, the interrupt service routine
can examine the flag bits.
Special Function Register PCON (Address 87_H)
Reset Value: 00_H
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
87_H SMOD PDS IDLS
SD
GF1 GF0 PDE IDLE PCON
The function of the shaded bit is not described in this section.
Symbol
PDS
IDLS
SD
GF1
Function
Power-Down Start bit
The instruction that sets the PDS flag bit is the last instruction before
entering the power down mode
Idle Start bit
The instruction that sets the IDLS flag bit is the last instruction before
entering the idle mode.
Slow Down mode bit
When set, the slow down mode is enabled
General purpose flag 1
User’s Manual
9-1
2001-05