C508_01 Datasheet, PDF (118/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.3.2.3 CAPCOM Unit Operating Mode 1
Using Compare Timer 1 in operating mode 1, two symmetric output signals with constant
dead time t_OFF at each signal transition can be generated per channel. Figure 6-28
shows the operating mode 1 timing in detail.
Count Value
CT1+CT1OFF
CCP = 7
Period Reg.
CT1OF = 2
Offset Reg.
Start of CT1
9
88
777
7
6666
6
55
55
44
CT1
44
55
44
33
3333
22
222
1
11
0
0
t _OFF
t _OFF
t _OFF
CCx (CC = 5)
COINI Bit = 0
COUTx (CC = 5)
COINI Bit = 0
COUTx (CC = 5)
COINI Bit = 1
CC : content of the CCxH/CCxL compare registers
CCP : content of the CCPH/CCPL period register
CT1OF : content of the CT1OFH/CT1OFL offset registers
Time
Duty
Cycles:
29%
57%
57%
MCT04294
Figure 6-28 Compare Timer 1 with Offset not equal to 0 - Mode 1
In the example above, Compare Timer 1 counts from 0000_H up to 0007_H (value stored
in period register CCPH/CCPL) and then counts down again to 0000_H. The maximum
and minimum (0000_H) values of the Compare Timer 1 always occur once in the count
value sequence. In the example shown in Figure 6-28, the offset registers have a value
of 0002_H.
With the programming of the CMSEL1 or CMSEL0 registers, all affected compare
outputs are switched to push-pull mode and start driving an initial level defined by the
bits in SFR COINI.
In operating mode 0, two compare output signals, CCx and COUTx, are assigned to the
related CAPCOM channel. The compare outputs CCx change their state if a match of
Compare Timer 1 content and the corresponding compare register occurs. The compare
outputs COUTx change their state when a match of Compare Timer 1 content plus the
value stored in the offset registers and the corresponding compare register has
occurred. If the value in the offset register plus the value of the period register is less than
or equal to the value stored in the compare register, a static ‘1’ or a static ‘0’ (depending
User’s Manual
6-53
2001-05