C508_01 Datasheet, PDF (114/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
6.3.2 CAPCOM Unit Operation
On-Chip Peripheral Components
6.3.2.1 CAPCOM Unit Clocking Scheme
The CAPCOM unit is controlled by the 16-bit Compare Timer 1. Compare Timer 1 is the
timing base for all compare and capture capabilities of the CAPCOM unit. The input clock
for Compare Timer 1 is directly coupled to the system clock of the C508. Its frequency
can be selected via three bits of the CT1CON register in a range of 2 f_OSC up to f_OSC/64.
For the understanding of the following timing diagrams, Figure 6-25 shows the internal
clocking scheme of the CAPCOM unit. The internal input clock of the CAPCOM unit is a
symmetrical clock with 50% duty cycle. The clock transitions (edges) of the CAPCOM
internal input clock are used for different actions. At clock edge 1, the Compare Timer 1
is clocked to the next count value and with clock edge 2, the compare outputs CCx and
COUTx are toggled/set to the new logic level if required.
Input clock
of CT1
2f_OSC
1
2
1
2
min. 50 ns (@ 10 MHz oscillator clock)
f_OSC
1
2
f_OSC/2
1
2
f_OSC/4
1 increment/decrement of compare timer 1
2 change/modify logic level at CCx/COUTx
MCD04066
Figure 6-25 CAPCOM Unit Clocking Scheme
Generally, the CAPCOM clocking scheme shown above is also valid for the COMP
(Compare Timer 2) unit.
User’s Manual
6-49
2001-05