C508_01 Datasheet, PDF (257/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
OTP Memory Operation
10.6
Lock Bits Programming / Read
The C508-4E has two programmable lock bits which, when programmed according to
Table 10-3, provide four levels of protection for the on-chip OTP code memory.
Table 10-3 Lock Bit Protection Types
Lock Bits at D1, D0 Protection Protection Type
D1
D0
Level
1
1
Level 0 The OTP lock feature is disabled. During normal
operation of the C508-4E, the state of the EA pin is
not latched on reset.
1
0
Level 1 During normal operation of the C508-4E, MOVC
instructions executed from external program
memory are disabled from fetching code bytes from
internal memory. EA is sampled and latched on
reset. An OTP memory read operation is only
possible according to OTP verification mode 2.
Further programming of the OTP memory is
disabled (reprogramming security).
0
1
Level 2 Same as Level 1, but also OTP memory read
operation using OTP verification mode is disabled.
0
0
Level 3 Same as Level 2, but additionally external code
execution by setting EA = low during normal
operation of the C508-4E is no longer possible.
External code execution, initiated by an internal
program (for example, by an internal jump
instruction above the OTP memory boundary), is
still possible.
Note: ‘1’ means that the lock bit is unprogrammed; ‘0’ means that lock bit is
programmed.
For a, OTP verify operation at protection Level 1, the C508-4E must be put into the OTP
verification mode.
If a device is programmed with protection Level 2 or 3, it is no longer possible to verify
the OTP contents of a customer rejected (FAR) OTP device.
When a protection level has been activated by programming of the lock bits, the basic
programming mode must be left for activation of the protection mechanisms. This means
that after the activation of a protection level, further OTP program/verify operations are
still possible if the basic programming mode is maintained.
User’s Manual
10-11
2001-05