C508_01 Datasheet, PDF (29/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Memory Organization
3.4.2 Accesses to XRAM using the DPTR (16-bit Addressing Mode)
The XRAM can be accessed by two read/write instructions, which use the 16-bit DPTR
for indirect addressing. These instructions are:
– MOVX
– MOVX
A, @DPTR (Read)
@DPTR, A (Write)
For accessing the XRAM, the effective address stored in DPTR must be in the range of
FC00_H to FFFF_H.
3.4.3
Accesses to XRAM using the Registers R0/R1 (8-bit Addressing
Mode)
The 8051 architecture also provides instructions for accesses to the external data
memory range which use only an 8-bit address (indirect addressing with registers R0 or
R1). The instructions are:
– MOVX
MOVX
A, @Ri
@Ri, A
(Read)
(Write)
A special page register is implemented in the C508 to enable accessing the XRAM with
the MOVX @Ri instructions as well; that is, XPAGE serves the same function for the
XRAM as Port 2 does for external data memory.
Special Function Register XPAGE (Address 91_H)
Reset Value: 00_H
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
91_H
.7
.6
.5
.4
.3
.2
.1
.0 ^XPAGE
Bit
XPAGE.7-0
Function
XRAM high address
XPAGE.7-0 is the address part A15-A8 when 8-bit MOVX
instructions are used to access internal XRAM.
Figure 3-2 to Figure 3-4 show the dependencies of XPAGE and Port 2 addressing in
order to illustrate the differences in accessing XRAM, external RAM, or the use of Port 2
as an I/O-port.
User’s Manual
3-5
2001-05