C508_01 Datasheet, PDF (153/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.3.4.2 Signal Generation in Multi-Channel PWM Modes
The multi-channel PWM modes of the C508 use the pins CCx and COUTx for compare
output signal generation. Before signal generation of a multi-channel PWM mode can be
started, the COINI register should be programmed with the logic value of the multi-
channel PWM inactive phase. After this, the output pins which are required for the multi-
channel PWM signal generation must be programmed to operate as compare outputs by
writing the mode select registers CMSEL0 and CMSEL1. Table 6-9 shows the CMSEL0/
CMSEL1 register bits which are required for the full operation of the multi-channel PWM
modes.
Table 6-9 Programming of Multi-Channel PWM Compare Outputs
Multi-Channel PWM Mode
CMSEL1
CMSEL0
Block commutation /
6-phase multi-channel PWM
XXXX Y011_B
Y011 Y011_B
5-phase multi-channel PWM
4-phase multi-channel PWM
Y010 Y011_B
Y010 Y001_B
Note: The abbreviation “X” means don’t care. The abbreviation “Y” (bit CMSELx.3)
represents the burst mode bit. If Y = 0 the signal generation at the COUTx pins is
controlled by Compare Timer 1. If Y = 1 the signal generation at the COUTx pins
is also controlled by Compare Timer 1 but modulated by Compare Timer 2.
Output Signals During the Active Phase
An active phase of a compare output signal in multi-channel PWM mode can be
controlled either by the CAPCOM unit (Compare Timer 1) and/or modulated by Compare
Timer 2. The selection is done by bit CMSELx.3 (see note below Table 6-9).
Figure 6-34 shows the different possibilities for controlling the active phase of a
compare output signal using Compare Timer 1. Compare Timer 1 may operate either in
mode 0 or mode 1. In multi-phase mode, the block commutation logic switches from one
state to the next state when Compare Timer 1 reaches the value 0000_H. As an active
phase always lasts for two states, the duration of an active phase is determined by
Compare Timer 1 reaching 0000_H twice.
As shown in Figure 6-34a, a compare output signal CCx or COUTx of a CAPCOM
channel is either at low or high level during the whole active phase when the value stored
in the Compare Timer 1 offset registers (CT1OFH, CT1OFL) and the value stored in its
compare registers (CCHx, CCLx) is equal 0000_H. When the compare value is not equal
0000_H and less or equal the period value, the active phase of the related compare output
signal CCx or COUTx is controlled by the CAPCOM unit as shown in Figure 6-34b.
User’s Manual
6-88
2001-05