C508_01 Datasheet, PDF (53/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
External Bus Interface
ROM verification mode 1 is selected if the inputs PSEN, ALE, EA, and RESET are put
to the specified logic level. Then, the 15-bit address of the internal ROM byte to be read
is applied to the Port 1 and Port 2 lines. After a delay, Port 0 outputs the content of the
addressed ROM cell. In ROM verification mode 1, the C508 must be provided with a
system clock at the XTAL pins and pull-up resistors on the Port 0 lines.
4.7.2 Protected ROM/OTP Mode
If the C508-4R ROM is protected by mask (or C508-4E OTP is used in protection
level 1), ROM/OTP verification mode 2 is used to verify the contents of the ROM, as
shown in Figure 4-5. Please refer the AC specifications in the C508 Data Sheet for
detailed timing characteristics of the ROM verification modes.
RESET
1st ALE pulse
ALE ^{after RESET}
12TCL
6TCL
Port 0
Latch
Data for
Addr. 0
Latch
Data for
Addr. 1
Latch
Data for
Addr. 2
Data for Ad.
X _*16-1
Latch
Data for
Addr. X _*16
Latch
Data for
Addr. X _*16+1
P3.5
Inputs: ALE = V_SS
PSEN, EA = V_IH / V_IH2
RESET =
Verify Result for previous
16 bytes of data:
Low: Verify Error
High: Verify OK
Note: Please refer to C 508 data sheet for the definition of TCL.
MCS04097
Figure 4-5 ROM Verification Mode 2
ROM/OTP verification mode 2 is selected if the inputs PSEN, EA, and ALE are put to the
specified logic levels. When RESET goes inactive, the ROM/OTP verification mode 2
sequence is started. The C508 outputs an ALE signal with a period of 12TCL and
expects data bytes at Port 0. The data bytes at Port 0 are assigned to the ROM
addresses in the following way:
User’s Manual
4-11
2001-05