C508_01 Datasheet, PDF (193/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.5.3 A/D Converter Clock Selection
The ADC uses two clock signals for operation: the conversion clock f_ADC (= 1/t_ADC) and
the input clock f_IN (= 1/t_IN). f_ADC is derived from the C508 system clock, 2 × f_OSC, which
is twice the crystal frequency applied at the XTAL pins via the ADC clock prescaler as
shown in Figure 6-50. The input clock f_IN is equal to 2 × f_OSC. The conversion clock f_ADC
is limited to a maximum frequency of 2 MHz. Therefore, the ADC clock prescaler must
be programmed to a value which ensures that the conversion clock does not exceed
2 MHz. The prescaler ratio is selected by the bits ADCL1 and ADCL0 of SFR ADCON1.
The table in Figure 6-50 shows the prescaler ratio which must be selected by ADCL1
and ADCL0 for typical system clock rates. Up to 8 MHz external crystal frequency, the
selected prescaler ratio must be at least 8. Between 8 MHz and 10 MHz, a prescaler ratio
of at least 16 must be selected. A prescaler ratio of 32 can used for any of the above
frequency ranges. A prescaler ratio of 4 should be used only when the C508 is operating
in slowdown mode.
2f_OSC
ADCL1
÷4
ADCL0
÷8
÷ 16
÷ 32
MUX
Conversion Clock f_ADC
Input Clock f_IN
A/D
Converter
Condition: f_{ADC max} = 2 MHz f_IN = 2f_OSC = 4 TCL¹⁾
Oscillator Clock
Rate (f_OSC)
5 MHz
8 MHz
10 MHz
f_IN
[MHz]
10
16
20
Prescaller
Ratio
÷8
÷8
÷ 16
f_ADC
[MHz]
1.25
2
1.25
ADCL1
0
0
1
1) _{Note: Please refer to the C508 Data Sheet for the definition of TCL.}
ADCL0
1
1
0
MCB04102
Figure 6-50 A/D Converter Clock Selection
User’s Manual
6-128
2001-05