C508_01 Datasheet, PDF (112/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Both compare timers start counting from 0000_H upwards to a count value stored in the
period registers. If the value stored in the period register is reached, they are reset
(operating mode 0, both compare timers) or the count direction is changed from up-
counting to down-counting (operating mode 1, only Compare Timer 1) Using operating
mode 0, edge aligned PWM signals can be generated. Using operating mode 1, center
aligned PWM signals can be generated. Compare Timer 1 can be programmed for both
operating modes while Compare Timer 2 always works in operating mode 0 with one
output signal COUT3. Figure 6-24 a) and c) show the function of these basic operating
modes.
Compare Timer 1 has an additional 16-bit offset register, which consists of the high byte
stored in CT1OFH and the low byte stored in CT1OFL. If the value stored in CT1OFF is
0, the compare timer operates as shown in Figure 6-24 a) and c). If the value stored in
CT1OFF is not zero, the compare timer operates as shown in Figure 6-24 b) and d). In
operating mode 0, Compare Timer 1 is always reset after its value has been equal to the
value stored in period register. In operating mode 1, the count direction of the compare
timer is changed from up- to down-counting when its value has reached the value stored
in the period register. The count direction is changed from down- to up-counting when
the compare timer value has reached 0000_H. Generally, the compare outputs CCx are
always assigned to a match condition with the compare timer value directly, where as
the compare outputs COUTx are assigned to a match condition with the compare timer
value plus the offset value. Therefore, signal waveforms with non-overlapping signal
transitions as shown in Figure 6-24 b) and d) can be generated.
Further, the initial logic output level of the CAPCOM channel outputs can be selected in
compare mode. This allows waveforms to be generated with inverting signal polarities.
In capture mode of the CAPCOM unit, the value of Compare Timer 1 is stored in the
capture registers on a signal transition at pins CCx.
The compare unit COMP is a 10-bit compare unit which can be used to generate a Pulse
Width Modulated signal. This PWM output signal drives the output pin COUT3. In burst
mode and in the PWM modes, the output of the COMP unit can be switched to the
COUTx outputs.
The block commutation control logic allows to generate versatile multi-channel PWM
output signals. In one of these modes, the block commutation mode, signal transitions
at the three external interrupt inputs are used to trigger the PWM signal generation logic.
Depending on these signal transitions, the six I/O lines of the CAPCOM unit, which are
decoupled in block commutation mode from the three Capture/Compare channels, are
driven as static or PWM modulated outputs. CAPCOM channel 0 can be used in block
commutation mode for a capture operation (speed measurement) which is triggered by
each transition at the external interrupt inputs.
Further, the multi-channel PWM mode signal generation can be also triggered by the
period of Compare Timer 1. These operating modes are referenced as multi-channel
PWM modes.
User’s Manual
6-47
2001-05