C508_01 Datasheet, PDF(54/267 Page) Infineon Technologies AG – 8-Bit CMOS Microcontroller

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C508_01 Datasheet, PDF (54/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

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C508

External Bus Interface

1. Data Byte = contents of internal ROM/OTP address 0000H

2. Data Byte = contents of internal ROM/OTP address 0001H

3. Data Byte = contents of internal ROM/OTP address 0002H

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16. Data Byte = contents of internal ROM/OTP address 000FH

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The C508 does not output any address information during the ROM/OTP verification

mode 2. The first data byte to be verified is always the byte which is assigned to the

internal ROM address 0000H and must be put onto the data bus with the falling edge of

RESET. With each following ALE pulse, the ROM/OTP address pointer is internally

incremented and the expected data byte for the next ROM address must be delivered

externally.

Between two ALE pulses, the data at Port 0 is latched (at 6TCL after ALE rising edge)

and is compared internally with the ROM/OTP contents of the actual address. If a verify

error is detected, the error condition is stored internally. After each 16th data byte, the

cumulated verify result (pass or fail) of the last 16 verify operations is output at P3.5. This

means that P3.5 stays at a static level (low for fail and high for pass) while the next

16 bytes are checked. The output of P3.5 will be updated according to the cumulated

verify result of the previous 16 bytes of data. In ROM verification mode 2, the C508 must

be provided with a system clock at the XTAL pins.

Figure 4-6 shows an application example of external circuitry which allows verification

of a protected ROM inside the C508-4R in ROM/OTP verification mode 2. When RESET

goes inactive, the C508 starts the ROM/OTP verify sequence. Its ALE is clocking a 15-bit

address counter. This counter generates the addresses for an external EPROM which is

programmed with the contents of the internal (protected) ROM/OTP. The verify detect

logic typically displays the state of the verify error output at P3.5. P3.5 can be latched

with the falling edge of ALE.

The CY signal of the address counter indicates to the verify detect logic the end of the

internal ROM verification.

Userâs Manual

4-12

2001-05

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