C508_01 Datasheet, PDF (183/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.4.6 Details about Modes 2 and 3
Eleven bits are transmitted through TxD or received through RxD: a start bit (0), eight
data bits (LSB first), a programmable 9^th data bit, and a stop bit (1). On transmission, the
9^th data bit (TB8) can be assigned the value of ‘0’ or ‘1’. On reception, the 9^th data bit
goes into RB8 in SCON. The baudrate is programmable to either 1/16 or 1/32 the
oscillator frequency in Mode 2 (When bit SMOD in SFR PCON (87_H) is set, the baudrate
is f_OSC/16). In Mode 3, the baudrate clock is generated by Timer 1, which is incremented
by a rate of f_OSC/6 or by the internal baudrate generator.
Figure 6-47 shows a functional diagram of the serial port in Modes 2 and 3. The receive
portion is exactly the same as in Mode 1. The transmit portion differs from Mode 1 only
in the 9^th bit of the transmit shift register. The associated timings for transmit/receive are
illustrated in Figure 6-48.
Transmission is initiated by any instruction that uses SBUF as a destination register. The
“Write-to-SBUF” signal also loads TB8 into the 9^th bit position of the transmit shift register
and flags the TX control unit that a transmission is requested. Transmission starts at the
next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the
divide-by-16 counter, not to the “Write-to-SBUF” signal.)
Transmission begins with the activation of SEND, which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that. The first shift clocks a ‘1’ (the stop
bit) into the 9^th bit position of the shift register. Thereafter, only ‘0’s are clocked in. Thus,
as data bits shift out to the right, ‘0’s are clocked in from the left. When TB8 is at the
output position of the shift register, the stop bit is just to the left of TB8, and all positions
to the left of that contain ‘0’s. This condition flags the TX control unit to do one last shift
and then deactivate SEND and set TI. This occurs at the 11^th divide-by-16 rollover after
“Write-to-SBUF”.
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times the established baudrate. When a transition is detected,
the divide-by-16 counter is immediately reset, and 1FF_H is written to the input shift
register.
At the 7^th, 8^th and 9^th counter states of each bit time, the bit detector samples the value
of RxD. The value accepted is the value that was seen in at least two of the three
samples. If the value accepted during the first bit time is not ‘0’, the receive circuits are
reset and the unit goes back to looking for another 1-to-0 transition. If the start bit proves
valid, it is shifted into the input shift register, and reception of the rest of the frame will
proceed.
As data bit come from the right, ‘1’s shift out to the left. When the start bit arrives at the
leftmost position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags
the RX control block to do one last shift, load SBUF and RB8, and to set RI. The signal
to load SBUF and RB8, and to set RI, will be generated if, and only if, the following
conditions are met at the time the final shift pulse is generated:
User’s Manual
6-118
2001-05