C508_01 Datasheet, PDF (135/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Capture/Compare Interrupt Request Flags/Register
The interrupt flags of the CAPCOM capture/compare match and Compare Timer 1
interrupt are located in the register CCIR. All CAPCOM capture/compare match interrupt
flags are set by hardware and must be cleared by software. A capture/compare match
interrupt is generated by setting of a CCxR bit (x = 0-2) if the corresponding enable bits
are set. The Compare Timer 1 interrupt is triggered by the CT1FP or CT1FC bits of SFR
CCIR.
Special Function Register CCIR (Address E5_H)
Reset Value: 00_H
Bit No. MSB
7
6
5
E5_H CT1FP CT1FC CC2F
4
CC2R
3
CC1F
2
CC1R
1
CC0F
LSB
0
CC0R
CCIR
CAPCOM
Channel 2
CAPCOM
Channel 1
CAPCOM
Channel 0
Bit
CT1FP
CT1FC
Function
Compare Timer 1 period flag
Compare Timer 1 operating mode 0: CT1FP is set if Compare Timer 1
reaches the period value.
Compare Timer 1 operating mode 1: CT1FP is set if Compare Timer 1
reaches the period value and changes the count direction from up- to
down counting
Bit CT1FP must be cleared by software. If Compare Timer 1 interrupt
is enabled, the setting of CT1FP will generate a Compare Timer 1
interrupt.
Compare Timer 1 count direction change flag
This flag can only be set if Compare Timer 1 runs in operating mode 1
(CTM = 1). CT1FC is set when Compare Timer 1 reaches count value
0000_H and changes the count direction from down- to up-counting. If
Compare Timer 1 interrupt is enabled, the setting of CT1FC will
generate a Compare Timer 1 interrupt.
Bit CT1FC must be cleared by software.
User’s Manual
6-70
2001-05