C508_01 Datasheet, PDF (223/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Interrupt System
7.4
Interrupt Handling
The interrupt flags are sampled at S5P2 in each machine cycle. The sampled flags are
polled during the following machine cycle. If one of the flags was in a set condition at
S5P2 of the preceeding cycle, the polling cycle will find it and the interrupt system will
generate an LCALL to the appropriate service routine, provided this hardware-generated
LCALL is not blocked by any of the following conditions:
1. An interrupt of equal or higher priority is already in progress.
2. The current (polling) cycle is not in the final cycle of the instruction in progress.
3. The instruction in progress is RETI or any write access to registers IEN0/IEN1 or IP0/
IP1.
Any of these three conditions will block the generation of the LCALL to the interrupt
service routine. Condition 2 ensures that the instruction in progress is completed before
vectoring to any service routine. Condition 3 ensures that if the instruction in progress is
RETI or any write access to registers IEN0/IEN1 or IP0/IP1, then at least one more
instruction will be executed before any interrupt is vectored to; this delay guarantees that
changes of the interrupt status can be observed by the CPU.
The polling cycle is repeated with each machine cycle, and the values polled are the
values that were present at S5P2 of the previous machine cycle. Note that if any interrupt
flag is active but not being responded to for one of the conditions already mentioned, or
if the flag is no longer active when the blocking condition is removed, the denied interrupt
will not be serviced. In other words, the fact that the interrupt flag was once active but
not serviced is not remembered. Every polling cycle interrogates only the pending
interrupt requests.
The polling cycle/LCALL sequence is illustrated in Figure 7-6.
C1
C2
C3
C4
C5
Interrupt is
latched
Interrupts
are polled
Long Call to Interrupt
Vector Address
Interrupt
Routine
MCT04086
Figure 7-6 Interrupt Response Timing Diagram
Note that if an interrupt of a higher priority level goes active prior to S5P2 in the machine
cycle labeled C3 in Figure 7-6 then, in accordance with the above rules, it will be
vectored to during C5 and C6 without any instruction for the lower priority routine to be
executed.
User’s Manual
7-25
2001-05