C508_01 Datasheet, PDF (198/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.5.5 A/D Converter Calibration
The C508 A/D Converter includes hidden internal calibration mechanisms which assure
a safe functionality of the A/D Converter according to the DC characteristics. The A/D
Converter calibration is implemented in a way that a user program which executes A/D
conversions is not affected by its operation. Further, the user program has no control
over the calibration mechanism. The calibration itself executes two basic functions:
– Offset calibration: correction of offset errors of comparator and the capacitor
network
– Linearity calibration: correction of the binary-weighted capacitor network
The A/D Converter calibration operates in two phases. The first phase is the calibration
after a reset operation and the second is the calibration at each A/D conversion. The
calibration phases are controlled by a state machine in the A/D Converter. This state
machine executes the calibration phases and stores the calibration results dynamically
in a small calibration RAM.
After a reset operation, the A/D calibration is automatically started. In this reset
calibration phase which takes 3328 f_ADC clocks, alternating offset and linearity
calibration is executed. Therefore, at 8 MHz oscillator frequency, and with a default
prescaler value of 8, a reset calibration time of approximately 1.664 ms is reached. For
achieving a proper reset calibration, the f_ADC prescaler value must satisfy the condition
f_{ADC max} ≤ 2 MHz. If this condition is not met, at a specific oscillator frequency with the
default prescaler value after reset, the f_ADC prescaler must be adjusted immediately after
reset by setting bits ADCL1 and ADCL0 in SFR ADCON1 to a suitable value. It is also
recommended to have the proper voltages, as specified in the Data Sheet, applied at the
V_AREF and V_AGND pins before the reset calibration has started.
After the reset calibration phase, the A/D Converter is calibrated according to its DC
characteristics. Nevertheless, during the reset calibration phase, single or continuous A/
D conversion can be executed. In this case, it must be regarded that the reset calibration
is interrupted and continued after the end of the A/D conversion. Therefore, interrupting
the reset calibration phase by A/D conversions extends the total reset calibration time. If
the specified total unadjusted error (TUE) needs to be valid for an A/D conversion, it is
recommended to start the first A/D conversion after reset when the reset calibration
phase has been completed. Depending on the oscillator frequency used, the reset
calibration phase can be possibly shortened by setting ADCL1 and ADCL0 (prescaler
value) to its final value immediately after reset.
After the reset calibration, a second calibration mechanism is initiated. This calibration is
coupled to each A/D conversion. With this second calibration mechanism, alternatively,
offset and linearity calibration values, which are stored in the calibration RAM, are
checked when an A/D conversion is executed. These values are corrected if required.
User’s Manual
6-133
2001-05