C508_01 Datasheet, PDF (106/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.2.2.4 Using Interrupts in Combination with the Compare Function
The compare service of registers CRC, T2CC1, T2CC2 and T2CC3 are assigned to
alternate output functions at port pins P5.0 to P5.3. Another option of these pins is that
they can be used as external interrupt inputs. However, when using the port lines as
compare outputs then the input line from the port pin to the interrupt system is
disconnected (but the pin’s level can still be read under software control). Thus, a
change of the pin’s level will not cause a setting of the corresponding interrupt flag. In
this case, the interrupt input is directly connected to the (internal) compare signal thus
providing a compare interrupt.
The compare interrupt can be used very effectively to change the contents of the
compare registers or to determine the level of the port outputs for the next “compare
match”. The principle is that the internal compare signal (generated at a match between
timer count and register contents) not only manipulates the compare output but also sets
the corresponding interrupt request flag. Thus, the current task of the CPU is interrupted
if the priority of the Compare interrupt is higher than the present task priority and the
corresponding interrupt service routine is called. This service routine then sets up all the
necessary parameters for the next compare event.
Advantages when Using Compare Interrupts
First, there is no danger of unintentional overwriting a Compare register before a match
has been reached. This could happen when the CPU writes to the compare register
without knowing about the actual Timer 2 count.
Second, and the most interesting advantage of the compare feature, is that the output
pin is exclusively controlled by hardware; therefore, it is completely independent from
any service delay which in real time applications could be disastrous. The compare
interrupt in turn is not sensitive to such delays since it loads the parameters for the next
event. This in turn is supposed to happen after a sufficient amount of time.
Please note the following special case where a program using compare interrupts could
show a “surprising” behavior.
The configuration has already been mentioned in the description of compare mode 1.
The fact that the compare interrupts are transition activated becomes important when
driving Timer 2 with a slow external clock. In this case it should be carefully considered
that the compare signal is active as long as the Timer 2 count is equal to the contents of
the corresponding compare register, and that the compare signal has a rising and a
falling edge. Furthermore, the “shadow latches” used in compare mode 1 are transparent
while the compare signal is active.
Thus, with a slow input clock for Timer 2, the comparator signal is active for a long time
(i.e. high number of machine cycles) and therefore a fast interrupt controlled reload of
the compare register could not only change the “shadow latch” - as probably intended -
but also the output buffer.
User’s Manual
6-41
2001-05