C508_01 Datasheet, PDF (226/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Interrupt System
a) Level-Activated Interrupt
P3.x/INTx
Low-Level Threshold
b) Transition-Activated Interrupt
e.g. P3.x/INTx
> 1 Machine Cycle
> 1 Machine Cycle
High-Level Threshold
> 1 Machine Cycle
Low-Level Threshold
MCT01921
Transition to
be detected
Figure 7-7 External Interrupt Detection
7.6
Interrupt Response Time
If an external interrupt is recognized, its corresponding request flag is set at S5P2 in
every machine cycle. The value is not polled by the circuitry until the next machine cycle.
If the request is active and conditions are right for it to be acknowledged, a hardware
subroutine call to the requested service routine will be the next instruction to be
executed. The call itself takes two cycles. Thus, a minimum of three complete machine
cycles will elapse between activation and external interrupt request and the beginning of
execution of the first instruction of the service routine.
A longer response time would be obtained if the request is blocked by one of the three
previously listed conditions. If an interrupt of equal or higher priority is already in
progress, the additional wait time obviously depends on the nature of the other interrupt's
service routine. If the instruction in progress is not in its final cycle, the additional wait
time cannot be more than three cycles since the longest instructions (MUL and DIV) are
only four cycles long; and, if the instruction in progress is RETI or a write access to
registers IEN0, IEN1 or IP0, IP1 the additional wait time cannot be more than five cycles
(a maximum of one more cycle to complete the instruction in progress, plus four cycles
to complete the next instruction, if the instruction is MUL or DIV).
Thus, in a single interrupt system, the response time is always more than three cycles
and fewer than nine cycles.
User’s Manual
7-28
2001-05