C508_01 Datasheet, PDF (131/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Compare Timer 1 Offset Registers
The CT1OFH and CT1OFL registers contain the value for the Compare Timer 1.
CT1OFH holds the high byte of the 16-bit offset value and CT1OFL holds the low byte.
For the detection of a compare match event, which results in changing polarity of a
COUTx compare output signal, the content of CT1OFH/CT1OFL is always added to the
actual value of the Compare Timer 1. The value stored in the offset registers has no
effect on the signal generation at the CCx compare outputs.
If the Compare Timer 1 offset registers are written, shadow latches are always loaded.
The content of these shadow latches is transferred to the real registers when STE1 is
set and the Compare Timer 1 reaches its period value or count value 0000_H. When the
Compare Timer 1 offset registers are read, shadow latches are always accessed.
Special Function Register CT1OFL (Address E6_H)
Special Function Register CT1OFH (Address E7_H)
Reset Value: 00_H
Reset Value: 00_H
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
E6_H
.7
.6
.5
.4
.3
.2
.1 LSB CT1OFL
E7_H MSB .6
.5
.4
.3
.2
.1
.0 CT1OFH
Bit
CT1OFL.7 - 0
CT1OFH.7 - 0
Function
8-bit Compare Timer 1 offset value, low byte
The 8-bit value in the CT1OFL register is the low byte of the offset
value for Compare Timer 1 (shadow latch).
8-bit Compare Timer 1 offset value, high byte
The 8-bit value in the CT1OFH register is the high byte of the offset
value for Compare Timer 1 (shadow latch).
To generate correct dead times for PWM signals, the offset value stored in CT1OFH/
CT1OFL must be lower than the values stored in the compare registers.
User’s Manual
6-66
2001-05