C508_01 Datasheet, PDF (78/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.1.4 Port Timing
When executing an instruction that changes the value of a port latch, the new value
arrives at the latch during S6P2 of the final cycle of the instruction. However, port latches
are only sampled by their output buffers during Phase 1 of any clock period (during
Phase 2 the output buffer holds the value it noticed during the previous Phase 1).
Consequently, the new value in the port latch will not appear at the output pin until the
next Phase 1, which will be at S1P1 of the next machine cycle.
When an instruction reads a value from a port pin (that is: MOV A, P1), the port pin is
actually sampled in State 5 Phase 1 or Phase 2, depending on the port and the
alternative functions. Figure 6-8 illustrates this port timing. It must be noted that this
mechanism of sampling once per machine cycle is also used if a port pin is to detect an
“edge”. For example, when used as counter input. In this case, an “edge” is detected
when the sampled value differs from the value that was sampled the cycle before.
Therefore, certain requirements must be met on the pulse length of signals in order to
avoid signal “edges” not being detected. The minimum time period of high and low level
is one machine cycle, which guarantees that this logic level is noticed by the port at least
once.
XTAL2
S4
S5
S6
S1
S2
S3
P1 P2 P1 P2 P1 P2 P1 P2 P1 P2 P1 P2
Input sampled:
e.g.: MOV A, P1
or
P1 active
(driver transistor)
Port
Old Data
New Data
MCT04049
Figure 6-8 Port Timing
User’s Manual
6-13
2001-05