C508_01 Datasheet, PDF (235/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Fail Save Mechanisms
is available from the RC oscillator. This internal Oscillator Watchdog reset has the same
effect as an externally applied reset signal with the following exceptions: The Watchdog
Timer Status flag WDTS is not reset (the Watchdog Timer is, however, stopped); and bit
OWDS is set. This allows the software to examine error conditions detected by the
Oscillator Watchdog unit even if an oscillator failure occurred in the meantime.
If the frequency derived from the on-chip oscillator is again higher than the reference, the
Oscillator Watchdog starts a final reset sequence which takes typically 1 ms. Within that
time, the system clock is still supplied by the RC oscillator and the part is held in reset.
This allows a reliable stabilization of the on-chip oscillator. When this happens, the PLL
will be locked and its clock output will be switched over as the system clock. After that,
the Oscillator Watchdog releases its internal reset request. If no other reset is applied at
this time, the part will start program execution. If an external reset or a Watchdog Timer
reset is active, however, the device will retain the reset state until the other reset request
disappears.
Furthermore, the status flag OWDS is set if the Oscillator Watchdog was active. The
status flag can be evaluated by software to detect that a reset was caused by the
Oscillator Watchdog. The flag OWDS can be set or cleared by software. An external
reset request, however, also resets OWDS (and WDTS).
The RC oscillator, the on-chip oscillator, and the PLL are stopped if software power-
down mode is activated. Both oscillators and the PLL are again started in power-down
mode when a low level is detected at either P3.2/INT0 or P5.7/INT7 and when bit EWPD
in SFR PCON1 is set (wake-up from power-down mode enabled). Bit WS in SFR PCON1
selects the wake-up source. In this case, the Oscillator Watchdog does not execute an
internal reset during startup of the on-chip oscillator. After the startup phase of the on-
chip oscillator, the Watchdog generates a power-down mode wake-up interrupt. Detailed
description of the wake-up from software power-down mode is given in Chapter 9.4.2.
User’s Manual
8-9
2001-05