C508_01 Datasheet, PDF (222/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Interrupt System
Table 7-2 Interrupts - Priority-within-Level
Interrupt Priority Bits
Interrupt Source Priority
Priority
Group of Interrupt
Group
High Priority
Low Priority
1
IP1.0 / IP0.0 IE0
–
IADC
–
High
2
IP1.1 / IP0.1 TF0
–
IEX2
–
3
IP1.2 / IP0.2 IE1
TRF +
IEX3
IEX7
BCERR
4
IP1.3 / IP0.3 TF1
CT2P
IEX4
IEX8
5
IP1.4 / IP0.4 RI + TI CCxR + IEX5
IEX9
CCxF
6
IP1.5 / IP0.5 TF2
CT1FP + IEX6
–
Low
CT1FC
Within a group, the leftmost interrupt is serviced first, then the second and the third and
the fourth, when available. The interrupt groups are serviced from top to bottom of the
table. A low-priority interrupt can itself be interrupted by a higher-priority interrupt, but not
by another interrupt of the same or a lower priority. An interrupt of the highest priority
level cannot be interrupted by another interrupt source.
If two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. If requests of the same priority level are
received simultaneously, an internal polling sequence determines which request is to be
serviced first. Thus, within each priority level there is a second priority structure which is
illustrated in Table 7-2.
The “priority-within-level” structure is used only to resolve simultaneous requests of the
same priority level.
User’s Manual
7-24
2001-05