C508_01 Datasheet, PDF (166/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Compare Timer 2 Controlled Active Phase at COUTx:
When bit ESMC in SFR CMSEL1 is set, Compare Timer 2 controlled output levels at
COUTx during the active phase of a multi-pole PWM timing are generated when the
following conditions are met:
– The 16-bit offset register of Compare Timer 1 must be 0000_H
(CT1OFH = CT1OFL = 00_H)
– The 16-bit capture/compare registers must be 0000_H
(CCL0 = CCH0 = CCL1 = CCH1 = CCL2 = CCH2 = 00_H)
– Bits CMSELx3 (x = 0-2) in the SFRs CMSEL0/CMSEL1 must be set
– Compare Timer 2 must be enabled and initialized for compare output signal
generation
Both, the CCx and the COUTx outputs can be controlled by Compare Timer 2.
A combination of outputs modulated by Compare Timer 1 and/or Compare Timer 2 is
supported.
6.3.4.6 Trap Function in Multi-Channel Block Commutation Mode
The trap function in block commutation mode is similar to the trap function described in
Chapter 6.3.2.7, “Trap Function of the CAPCOM Unit in Compare Mode”. But there
is one difference: when CTRAP becomes inactive (high), the CCx and COUTx outputs
are again switched back to the PWM pulse generation when Compare Timer 2 reaches
the count value 000_H (instead of Compare Timer 1 in all other modes).
All other trap functions of the multi-channel PWM modes are identical as described in
Chapter 6.3.2.7.
User’s Manual
6-101
2001-05