C508_01 Datasheet, PDF (179/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.4.5 Details about Mode 1
Ten bits are transmitted through TxD or received through RxD: a start bit (0), eight data
bits (LSB first), and a stop bit (1). On reception, the stop bit goes into RB8 in SCON. The
baudrate is determined either by the Timer 1 overflow rate or by the internal baudrate
generator.
Figure 6-45 shows a simplified functional diagram of the serial port in Mode 1. Timing
associated with transmit and receive is illustrated in Figure 6-46.
Transmission is initiated by an instruction that uses SBUF as a destination register. The
“Write-to-SBUF” signal also loads a ‘1’ into the 9^th bit position of the transmit shift register
and flags the TX control unit that a transmission is requested. Transmission starts at the
next rollover in the divide-by-16 counter. (Thus, the bit times are synchronized to the
divide-by-16 counter, not to the “Write-to-SBUF” signal).
The transmission begins with activation of SEND, which puts the start bit at TxD. One bit
time later, DATA is activated, which enables the output bit of the transmit shift register to
TxD. The first shift pulse occurs one bit time after that.
As data bits shift out to the right, ‘0’s are clocked in from the left. When the MSB of the
data byte is at the output position of the shift register, then the ‘1’ which was initially
loaded into the 9^th position is just to the left of the MSB, and all positions to the left of that
contain ‘0’s. This condition flags the TX control unit to do one last shift and then
deactivate SEND and set TI. This occurs at the 10^th divide-by-16 rollover after “Write-to-
SBUF”.
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of sixteen times the established baudrate. When a transition is
detected, the divide-by-16 counter is immediately reset. The input shift register is written
with 1FF_H and reception of the rest of the frame will proceed.
The sixteen states of the counter divide each bit time into 16^ths. At the 7^th, 8^th and 9^th
counter states of each bit time, the bit detector samples the value of RxD. The value
accepted is the value that was seen in at least two of the three samples. This is done for
the noise rejection. If the value accepted during the first bit time is not ‘0’, the receive
circuits are reset and the unit goes back to looking for another 1-to-0 transition. This is
to provide rejection or false start bits. If the start bit proves valid, it is shifted into the input
shift register, and reception of the rest of the frame will proceed.
As data bits come in from the right, ‘1’s shift out to the left. When the start bit arrives at
the leftmost position in the shift register, (which in Mode 1 is a 9-bit register), it flags the
RX control block to do one last shift, load SBUF and RB8, and set RI. The signal to load
SBUF and RB8, and to set RI, will be generated if, and only if, the following conditions
are met at the time the final shift pulse is generated.
1. RI = 0, and
2. either SM2 = 0, or the received stop bit = 1
User’s Manual
6-114
2001-05