C508_01 Datasheet, PDF (45/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
External Bus Interface
4.1.2 Timing
The timing of the external bus interface, in particular the relationship between the control
signals ALE, PSEN, RD, WR and information on Port 0 and Port 2, is illustrated in
Figure 4-1 a) and b).
Data memory:
In a write cycle, the data byte to be written appears on Port 0 just
before WR is activated and remains there until after WR is
deactivated. In a read cycle, the incoming byte is accepted at Port 0
before the read strobe is deactivated.
Program memory: Signal PSEN functions as a read strobe.
4.1.3 External Program Memory Access
The external program memory is accessed under two conditions:
– whenever signal EA is active (low) or
– whenever the program counter (PC) content is greater than 7FFF_H
When the CPU is executing out of external program memory, all eight bits of Port 2 are
dedicated to an output function and must not be used for general-purpose I/O. The
contents of the Port 2 SFR, however, are not affected. During external program memory
fetches, Port 2 lines output the high byte of the PC, and during accesses to external data
memory, they output either DPH or the Port 2 SFR (determined by whether external data
memory access is a MOVX @DPTR or a MOVX @Ri).
4.2
PSEN, Program Store Enable
The read strobe for external program memory fetches is PSEN. It is not activated for
internal program memory fetches. When the CPU is accessing external program
memory, PSEN is activated twice every instruction cycle (except during a MOVX
instruction) whether or not the byte fetched is actually needed for the current instruction.
When PSEN is activated, its timing is not the same as for RD. A complete RD cycle,
including activation and deactivation of ALE and RD, takes three oscillator periods. A
complete PSEN cycle, including activation and deactivation of ALE and PSEN, takes
1.5 oscillator periods. (The execution sequence for these two types of read cycles is
shown in Figure 4-1 a) and b).
4.3
Overlapping External Data and Program Memory Spaces
In some applications, it is desirable to execute a program from the same physical
memory that is used for storing data. In the C508, the external program and data memory
spaces can be combined by the logical-AND of PSEN and RD. A positive result from this
AND operation produces a low active read strobe that can be used for the combined
physical memory. As the PSEN cycle is faster than the RD cycle, the external memory
must be fast enough to adapt to the PSEN cycle.
User’s Manual
4-3
2001-05