C508_01 Datasheet, PDF (28/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Memory Organization
When bit XMAP1 in SFR SYSCON is set, during all accesses to XRAM, RD and WR
become active and Port 0 and Port 2 drive the actual address/data information which is
read/written from/to XRAM. This feature allows checking of the internal data transfers to
XRAM. When Ports 0 and 2 are used for I/O purposes, the XMAP1 bit should not be set;
otherwise, the I/O function of the Port 0 and Port 2 lines is interrupted.
After a reset operation, bit XMAP0 is set. This means that the accesses to XRAM are
generally disabled. In this case, all accesses using MOVX instructions within the address
range of FC00_H to FFFF_H generate external data memory bus cycles. When XMAP0 is
cleared, the access to XRAM is enabled and all accesses using MOVX instructions with
an address in the range of FC00_H to FFFF_H will access the internal XRAM.
Bit XMAP0 is hardware protected. If it is cleared once (that is, if internal XRAM access
enabled), it cannot be set by software. Only a reset operation will set the XMAP0 bit
again. This hardware protection mechanism is implemented by an asymmetric latch at
XMAP0 bit. An unintentional disabling of XRAM could be dangerous as indeterminate
values could be read from the external bus. To avoid this, the XMAP0 bit is forced to ‘1’
only by a reset operation. Additionally, during reset, an internal capacitor is charged. So
the reset status is a disabled XRAM. After a ‘0’ is written to XMAP0 bit (that is,
discharging the capacitor), it is not possible to set it back again to ‘1’ due to the charge
time of the capacitor. On the other hand, any distortion (such as a software hang up,
noise, etc.) also cannot charge this capacitor. Thus, the stable status is the enabled
XRAM.
The clear instruction for the XMAP0 bit should be integrated into the program
initialization routine before XRAM is used. In extremely noisy systems, the user may
have redundant clear instructions.
User’s Manual
3-4
2001-05