C508_01 Datasheet, PDF (147/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
power-down mode procedure. When CT2RES is cleared before software power
down mode is entered and a wake-up from power-down mode procedure has
been executed, the Compare Timer 2 is not reset. Depending on the state of bit
CT2R at power down mode entry, the Compare Timer 2 either stops (CT2R = 0)
or continues (CT2R = 1) counting after a wake-up from power-down mode
procedure. Further details of the power-down mode are described in Chapter 9.2.
Compare Timer 2 Period Registers
The Compare Timer 2 period registers CP2L/CP2H hold the 10-bit value for the
Compare Timer 2 period. When the Compare Timer 2 value is equal to the value stored
in the period register, the COUT3 signal changes from inactive to active state. If CP2H/
CP2L is written, only shadow latches are written. The content of these latches is
transferred to the real registers at compare timer count value 000_H, using bit STE2 of
SFR CT2CON.
When the Compare Timer 2 period registers CP2L/CP2H are read, the shadow registers
are always accessed.
Special Function Register CP2L (Address D2_H)
Special Function Register CP2H (Address D3_H)
Reset Value: 00_H
Reset Value: XXXXXX00_B
Bit No. MSB
LSB
7
6
5
4
3
2
1
0
D2_H
.7
.6
.5
.4
.3
.2
.1
.0 CP2L
D3_H
–
–
–
–
–
–
.1
.0 CP2H
Bit
CP2L.7 - 0
CP2H.1 - 0
–
Function
Compare Timer 2 period value, low byte
The CP2L register holds the lower 8 bits of the 10-bit period value for
Compare Timer 2 (shadow latch).
Compare Timer 2 period value, high bits
The CP2H register holds most significant two bits of the 10-bit period
value for Compare Timer 2 (shadow latch).
Reserved bits
User’s Manual
6-82
2001-05