C508_01 Datasheet, PDF (73/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.1.2.3 Port 2 Circuitry
As shown in Figure 6-3 and in Figure 6-5, the output drivers of Ports 0 and 2 can be
switched to an internal address or address/data bus for use in external memory
accesses. In this application, these two ports cannot be used as general purpose I/O,
even if not all address lines are used externally. The switching is done by an internal
control signal dependent on the input level at the EA pin and/or the contents of the
program counter. If the ports are configured as an address/data bus, the port latches are
disconnected from the driver circuit. During this time, the P0/P2 SFR remains
unchanged. As an address/data bus, Port 0 uses a pull-up FET as shown in Figure 6-3.
When a 16-bit address is used, Port 2 uses the additional strong pull-ups p1
(Figure 6-5a) to emit ‘1’s for the entire external memory cycle instead of the weak ones
(p2 and p3) used during normal port activity.
Read
Latch
Int. Bus
Write
to
Latch
D
Q
Bit
Latch
CLK
Q
Addr. Control ^VDD
MUX
Internal
Pull Up
Arrangement
Port
Pin
=1
Read
Pin
MCS04045
Figure 6-5 Port 2 Circuitry
Port 0 can be used for I/O functions if no external bus cycles are generated using data
or code memory accesses.
User’s Manual
6-8
2001-05