C508_01 Datasheet, PDF (240/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Power Saving Modes
The idle mode is entered by two consecutive instructions. The first instruction sets the
flag bit IDLE (PCON.0) and must not set bit IDLS (PCON.5). The following instruction
sets the start bit IDLS (PCON.5) and must not set bit IDLE (PCON.0). The hardware
ensures that a concurrent setting of both bits, IDLE and IDLS, does not initiate the idle
mode. Bits IDLE and IDLS will automatically be cleared after being set. If one of these
register bits is read, the value that appears is 0. This double instruction is implemented
to minimize the chance of unintentionally entering of the idle mode which would render
the Watchdog Timer’s task of system protection without effect.
Note: PCON is not a bit-addressable register, so the above mentioned sequence for
entering the idle mode is obtained by byte-handling instructions, as shown in the
following example:
ORL PCON,#00000001B
ORL PCON,#00100000B
;Set bit IDLE, bit IDLS must not be set
;Set bit IDLS, bit IDLE must not be set
The instruction that sets bit IDLS is the last instruction executed before going into idle
mode.
There are two ways to terminate the idle mode:
– The idle mode can be terminated by activating any enabled interrupt. The CPU
operation is resumed, the interrupt will be serviced, and the next instruction to be
executed after the RETI instruction will be the one following the instruction which
set the bit IDLS.
– The other way to terminate the idle mode is a hardware reset. Since the oscillator
is still running, the hardware reset must be held active only for two machine cycles
for a complete reset.
User’s Manual
9-4
2001-05