C508_01 Datasheet, PDF (69/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
6.1.2 Standard I/O Port Circuitry
Figure 6-1 is a functional diagram of a typical bit latch and I/O buffer which make up the
core of each of the five I/O-ports. The bit latch (one bit in the port’s SFR) is represented
as a type-D flip-flop which will clock in a value from the internal bus in response to a
“write-to-latch” signal from the CPU. The Q output of the flip-flop is placed on the internal
bus in response to a “read-latch” signal from the CPU. The level of the port pin itself is
placed on the internal bus in response to a “read-pin” signal from the CPU. Some
instructions that read from a port (that is, from the corresponding port SFR P0 to P4)
activate the “read-latch” signal, while others activate the “read-pin” signal.
Read
Latch
Int. Bus
Write
to
Latch
D
Q
Port
Latch
CLK
Q
Port
Driver
Circuit
Read
Pin
Figure 6-1 Basic Structure of a Port Circuitry
Port
Pin
MCS04041
User’s Manual
6-4
2001-05