C508_01 Datasheet, PDF (33/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Memory Organization
The register XPAGE provides the upper address byte for accesses to XRAM with MOVX
@Ri instructions. If the address formed by XPAGE and Ri points outside the XRAM
address range, an external access is performed. For the C508, the content of XPAGE
must be FC_H - FF_H in order to use the XRAM.
The software must distinguish two cases, if the MOVX @Ri instructions with paging will
be used:
a) Access to XRAM:
b) Access to external memory:
The upper address byte must be written to XPAGE
or P2; both writes select the XRAM address range.
The upper address byte must be written to P2;
XPAGE will be automatically loaded with the same
address in order to deselect the XRAM.
3.4.4 Reset Operation of the XRAM
The contents of the XRAM are not affected by a reset. After power-up, the contents are
undefined, while they remain unchanged during and after a reset, as long as the power
supply is not turned off. If a reset occurs during a write operation to XRAM, the effect on
the contents of a XRAM memory location depends on the cycle in which the active reset
signal is detected (MOVX is a two-cycle instruction):
Reset during 1^st cycle: The new value will not be written to XRAM. The old value is
not affected.
Reset during 2^nd cycle: The old value in XRAM is overwritten by the new value.
3.4.5 Behavior of Port 0 and Port 2
The behavior of Port 0 and Port 2 during a MOVX access depends on the control bits in
the SYSCON Register and on the state of Pin EA. Table 3-1 lists the various operating
conditions. It shows the following characteristics:
a) Use of P0 and P2 pins during the MOVX access.
Bus: The pins work as an external address/data bus. If (internal) XRAM is
accessed, the data written to the XRAM can be seen on the bus in debug
mode.
I/O: The pins work as Input/Output lines under control of their latch.
b) Activation of the RD and WR pin during the access.
c) Use of internal (XRAM) or external XDATA memory.
The shaded areas in Table 3-1 describe the standard operation for each C500 device
without on-chip XRAM.
User’s Manual
3-9
2001-05