C508_01 Datasheet, PDF (215/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Interrupt System
Special Function Register SCON (Address. 98_H)
MSB
Bit No. 9F_H
9E_H 9D_H
9C_H
9B_H 9A_H
98_H SM0 SM1 SM2 REN TB8 RB8
Reset Value: 00_H
LSB
99_H 98_H
TI
RI SCON
The shaded bits are not used for interrupt control.
Bit Function
TI
Serial interface transmitter interrupt flag
Set by hardware at the end of a serial data transmission. Must be cleared by
software.
RI
Serial interface receiver interrupt flag
Set by hardware if a serial data byte has been received. Must be cleared by
software.
The serial interface interrupt is generated by a logical OR of flag RI and TI in SFR
SCON. Neither of these flags is cleared by hardware when the service routine is
vectored to. In fact, the service routine will normally need to determine whether it was
the receive interrupt flag or the transmission interrupt flag which generated the interrupt,
and the corresponding bit will need to be cleared by software.
The interrupt request flags of the CAPCOM capture/compare match interrupt are
located in the register CCIR. All CAPCOM capture/compare match interrupt flags are set
by hardware and must be cleared by software. A capture/compare match interrupt is
generated with the setting of a CCxR bit (x = 0-2) if the corresponding enable bits are
set. These enable bits are contained in register CCIE. The Compare Timer 1 interrupt
request flags – CT1FP or CT1FC – are also located in the register CCIR. Each flag has
a corresponding enable bit which is located in the register CCIE. However, the Compare
Timer 2 interrupt request flag, CT2P, is located in register CT2CON. The CCU
emergency interrupt can be triggered by either bit TRF located in register TRCON or
by bit BCERR located in register BCON. Each flag has an enable bit. For bit TRF, it is
located in register CT1CON; whereas, for bit BCERR, it is found in register BCON.
User’s Manual
7-17
2001-05