C508_01 Datasheet, PDF (196/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Depending on the selected prescaler ratio (see Figure 6-50), three different
relationships between machine cycles and A/D conversion are possible. The A/D
conversion is started when SFR ADDATL is written with dummy data. This write
operation may take one or two machine cycles. In Figure 6-52, the instruction MOV
ADDATL,#0 starts the A/D conversion (machine cycle X-1 and X). The total A/D
conversion (sample, conversion, and calibration phase) is finished with the end of the
8^th, 16^th, 32^nd, or 64^th machine cycle after the A/D conversion start. In the next machine
cycle, the conversion result is written into the ADDAT registers; and this result can be
read in the same cycle (for example, MOV A, ADDATL). If continuous conversion is
selected (bit ADM set), the next conversion is started with the beginning of the machine
cycle which follows the write result cycle.
The BSY bit is set at the beginning of the first A/D conversion machine cycle and reset
at the beginning of the write result cycle. If continuous conversion is selected, BSY is set
again with the beginning of the machine cycle which follows the write result cycle.
The interrupt flag IADC is set at the end of the A/D conversion. If the A/D Converter
interrupt is enabled and the A/D Converter interrupt is prioritized to be serviced
immediately, the first instruction of the interrupt service routine will be executed in the
third machine cycle which follows the write result cycle. IADC must be reset by software.
Depending on the application, typically there are three methods to handle the A/D
conversion in the C508.
– Software delay
The machine cycles of the A/D conversion are counted and the program executes
a software delay (e.g. NOPs) before reading the A/D conversion result in the write
result cycle. This is the fastest method to get the result of an A/D conversion.
– Polling BSY bit
The BSY bit is polled and the program waits until BSY = 0. Attention: a polling JB
instruction which is two machine cycles long, possibly may not recognize the
BSY = 0 condition during the write result cycle in the continuous conversion mode.
– A/D conversion interrupt
After the start of an A/D conversion the A/D Converter interrupt is enabled. The
result of the A/D conversion is read in the interrupt service routine. If other C508
interrupts are enabled, the interrupt latency must be regarded. Therefore, this
software method is the slowest method to get the result of an A/D conversion.
Depending on the oscillator frequency of the C508 and the selected divider ratio of the
conversion clock prescaler, the total time of an A/D conversion is calculated according
to Figure 6-51 and Table 6-14. Figure 6-53 on the next page shows the minimum A/D
conversion time in relation to the oscillator frequency f_OSC. The minimum conversion
time is 6 µs and can be achieved at f_OSC of 8 (or whenever f_ADC = 2 MHz).
User’s Manual
6-131
2001-05