C508_01 Datasheet, PDF (61/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Reset and System Clock Operation
Although the Oscillator Watchdog provides a fast internal reset, it is also necessary to
apply the external reset signal when powering up to enable the following:
– Termination of Software Power-Down Mode
– Reset of the status flag OWDS that is set by the oscillator watchdog during the
power up sequence.
Fast reset of Port 1, that is the Compare/Capture pins, during power-on.
If a crystal or ceramic resonator is used for clock generation, the external reset signal
must be held active at least until the on-chip oscillator has started and the internal
watchdog reset phase is completed (after phase IV in Figure 5-2). When an external
clock generator is used, phase II is very short. Therefore, an external reset time of 1 ms
(typical) is sufficient in most applications.
Generally, an external capacitor can be connected to the RESET pin for reset time
generation at power-on.
Figure 5-3 is a close-up view of Phase 1 shown in Figure 5-2. When RESET is high after
V_DD is stable, Port 1 will be defined with its default value (high). All other ports will still
remain undefined for at most 34 µs.
V_DD
RESET
Port 1
Other
Ports
Undefined
(typ. 18 µs
max. 34 µs)
Figure 5-3 Fast Reset of Port 1 Pins
MCD04032
User’s Manual
5-5
2001-05