C508_01 Datasheet, PDF (63/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Reset and System Clock Operation
5.4
Clock Generation
The top-level view of the system clock generation of the C508 is shown in Figure 5-5.
f_RC or f_OSC
RC
f_RC
Osc
Freq
Comp.
XTAL1
On-Chip
f_OSC
XTAL2
Osc
PLL
Clkin
f_PLL
Clkout
Control
Logic
Lock
Lock
System
Clock
MCB04033
Figure 5-5 Block Diagram of the Clock Generation
The clock generation block consists of the RC oscillator, the on-chip oscillator, and the
PLL.
At power-on reset, the RC oscillator takes a shorter time to start in comparison to the on-
chip oscillator (typically 2 µs versus 10 ms). While the on-chip oscillator is still unstable,
the PLL remains unlocked. Thus, the RC clock is provided as the system clock.
When the on-chip oscillator has stabilized, the PLL locks within 1 ms, providing a clock
frequency twice that of the on-chip oscillator’s frequency. The system clock source is
now switched to the PLL clock.
External reset from the pin should be released only after this stage.
5.5
PLL Operation
Within 1 ms after stable oscillations of the input clock within the specified frequency
range, the PLL will be synchronous with this clock at a frequency twice that of the input
frequency. In other words, the PLL locks onto its input clock.
Since the PLL constantly adapts to the external clock to remain locked, the CPU clock
generated has a slight variation known as jitter. This jitter is irrelevant for longer time
periods. For short periods (one to four CPU clock cycles), it remains below 4%.
When the PLL detects a missing input clock signal, it releases the lock signal.
Consequently, an internal reset will be active until the PLL is locked again. This may
occur if the input clock is unstable or fails completely; for example, due to a broken
crystal. In this case, an Oscillator Watchdog reset will also occur.
User’s Manual
5-7
2001-05