C508_01 Datasheet, PDF (229/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Fail Save Mechanisms
8.1.1 Input Clock Selection
The input clock rate of the Watchdog Timer is derived from the system clock of the C508.
There is a prescaler available which is software selectable and defines the input clock
rate. This prescaler is controlled by bit WDTPSEL in the SFR WDTREL. Table 8-1
shows the resulting timeout periods at f_OSC = 5, 8, and 10 MHz.
Special Function Register WDTREL (Address 86_H)
Reset Value: 00_H
MSB
LSB
Bit No. 7
6
5
4
3
2
1
0
86_H
WDT
PSEL
Reload Value
WDTREL
Bit
WDTPSEL
WDTREL.6 - 0
Function
Watchdog Timer Prescaler Select bit
The Watchdog Timer is clocked through an additional divide-by-
16 prescaler when this bit is set.
Watchdog Timer Reload
Seven bit reload value for the high-byte of the Watchdog Timer.
This value is loaded to WDTH when a refresh is triggered by a
consecutive setting of the WDT and SWDT bits.
Table 8-1
WDTREL
00_H
80_H
7F_H
Watchdog Timer Time-Out Periods
Time-Out Period
Comments
f_OSC = 5 MHz f_OSC = 8 MHz f_OSC = 10 MHz
39.322 ms 24.576 ms
19.668 ms
This is the default value
629.146 ms 393.2 ms
314.573 ms Maximum time period
307.2 µs
192 µs
153.6 µs
Minimum time period
User’s Manual
8-3
2001-05