C508_01 Datasheet, PDF (227/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Fail Save Mechanisms
8
Fail Save Mechanisms
The C508 offers enhanced fail save mechanisms which allow automatic recovery from
software or hardware failure:
– A programmable Watchdog Timer (WDT) with variable time-out period from
153.6 µs to 314.573 ms at f_OSC = 10 MHz.
– An Oscillator Watchdog (OWD) which monitors the on-chip oscillator and forces the
microcontroller into reset state if the on-chip oscillator fails. It also provides the
clock for a fast internal reset after power-on.
8.1
Programmable Watchdog Timer
To protect the system against software failure, the user’s program must clear this
Watchdog Timer within a previously programmed time period. If the software fails to
refresh the Watchdog Timer periodically, an internal reset will be initiated. The software
can be designed so that the Watchdog times out if the program does not work properly.
lt also times out if a software error is based on a hardware-related problem.
The Watchdog Timer in the C508 is a 15-bit timer which is incremented by a count rate
of f_OSC/6 up to f_OSC/96. The machine clock of the C508 is divided by two prescalers. One
is a divide-by-two prescaler; the other is a divide-by-16 prescaler. To program the
Watchdog Timer overflow rate, the upper seven bits of the Watchdog Timer can be
written. Figure 8-1 shows the block diagram of the Watchdog Timer unit.
f_OSC/3
÷2
÷ 16
0
7
WDTL
WDT Reset-Request
OWDS WDTS -
-
-
-
External HW Reset
14
8
WDTH
IP0 (A9_H)
-
-
WDTPSEL
76
0
WDTREL (86_H)
Control Logic
-
WDT
-
-
-
-
-
- _{IEN0 (A8H)}
- SWDT -
-
-
-
-
- _{IEN1 (B8H)}
MCS04087
Figure 8-1 Block Diagram of the Programmable Watchdog Timer
User’s Manual
8-1
2001-05