C508_01 Datasheet, PDF (107/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
When using the CRC, an interrupt should be generated when the compare signal goes
active or inactive, depending on the status of bit I3FR in T2CON.
Initializing the interrupt to be negative transition triggered is advisable in the above case.
Then the compare signal is already inactive and any write access to the port latch
changes only the contents of the “shadow-latch”.
Note that for T2CC1 to T2CC3 registers, an interrupt is always requested when the
compare signal goes active.
The second configuration which should be noted is the compare function combined with
negative transition activated interrupts. lf the port latch of Port P5.0 contains a ‘1’, the
interrupt request flags IEX3 will immediately be set after enabling the compare mode for
the CRC register. The reason is that first the external interrupt input is controlled by the
pin’s level. When the compare option is enabled, the interrupt logic input is switched to
the internal compare signal, which carries a low level when no true comparison is
detected. So, the interrupt logic sees a 1-to-0 edge and sets the interrupt request flag.
An unintentional generation of an interrupt during compare initialization can be
prevented if the request flag is cleared by software after the compare is activated and
before the external interrupt is enabled.
User’s Manual
6-42
2001-05