C508_01 Datasheet, PDF (145/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Compare Timer 2 Control Register
The 10-bit Compare Timer 2 is controlled by the bits of the CT2CON register. With this
register the count mode, the timer input clock rate, and the compare timer reset function
is controlled.
Special Function Register CT2CON (Address F1_H)
Reset Value: 00010000_B
Bit No. MSB
7
6
5
4
3
F1_H CT2P ECT2O STE2 CT2RES CT2R
2
CLK2
1
CLK1
LSB
0
CLK0
CT2CON
Bit
CT2P
ECT2O
STE2
Function
Compare Timer 2 period flag
When the Compare Timer 2 value matches with the Compare Timer 2
period register value, bit CT2P is set. If the Compare Timer 2 interrupt
is enabled, the setting of CT2P will generate a Compare Timer 2
interrupt. Bit CT2P must be cleared by software.
Enable Compare timer 2 output
When ECT2O is cleared and Compare Timer 2 is running, output
COUT3 is put into the logic state as defined by bit COUT3I which is
located in SFR COINI.6. When ECT2O is set and Compare Timer 2
is running, the Compare Timer 2 output COUT3 is enabled and
outputs the PWM signal of the COMP unit.
COMP unit shadow latch transfer enable
When STE2 is set, the content of the Compare Timer 2 period and
compare latches (CP2H, CP2L, CMP2H, CMP2L) is transferred to its
real registers when Compare Timer 2 reaches the period value. After
the shadow transfer event, STE2 is reset by hardware.
User’s Manual
6-80
2001-05