C508_01 Datasheet, PDF (254/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
OTP Memory Operation
The basic programming mode is selected by executing the following steps:
– With a stable V_DD, a clock signal is applied to the XTAL pins; the RESET pin is set to
‘1’ level and the PSEN pin is set to ‘0’.
– PROG, PALE, PMSEL1 and EA/V_PP are set to ‘0’ level; PRD, PSEL, and PMSEL0 are
set to ‘1’.
– PSEL is switched from ‘1’ to ‘0’ level and thereafter PROG is switched to ‘1’.
– PMSEL1, 0 can now be changed; after EA/V_PP has been set to V_IH2 high level or to
V_PP, the OTP memory is ready for access.
The pins RESET and PSEN must stay at static signal levels ‘1’ and ‘0’ respectively
throughout the entire programming mode. With a falling edge of PSEL, the logic state of
PROG and EA/V_PP are internally latched. These two signals are now used as
programming write pulse signal (PROG) and as programming voltage input pin V_PP.
After the falling edge of PSEL, PSEL must stay at ‘0’ state during all programming
operations.
Note: If protection level 1 to 3 has been programmed (see Chapter 10.6) and the
programming mode has been left, it is no longer possible to enter the
programming mode!
10.4.2 OTP Memory Access Mode Selection
When the C508-4E has been put into the programming mode using the basic
programming mode selection, several access modes of the OTP memory programming
interface are available. The conditions for the different control signals of these access
modes are listed in Table 10-2.
Table 10-2 Access Modes Selection
Access Mode
EA/ PROG PRD
V_PP
Program OTP memory V_PP
H
byte
Read OTP memory byte V_IH H
Program OTP lock bits V_PP
H
Read OTP lock bits
V_IH H
Read OTP version byte V_IH H
PMSEL
10
HH
HL
LH
Address Data
(Port 2) (Port 0)
A0-A7
A8-A14
D0-D7
–
D1, D0 see
Table 10-3
Byte addr. D0-D7
of version
byte
The access modes from Table 10-2 are basically selected by setting the two PMSEL1,
0 lines to the required logic level. The PROG and PRD signal are the write and read
strobe signal. Data is transferred via Port 0 and addresses are applied to Port 2.
User’s Manual
10-8
2001-05