C508_01 Datasheet, PDF (211/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Interrupt System
The Timer 0 and Timer 1 interrupts are generated by TF0 and TF1 in register TCON,
which are set by a rollover in their respective timer/counter registers. When a timer
interrupt is generated, the flag that generated it is cleared by the on-chip hardware when
the service routine is vectored to.
Special Function Register T2CON (Address C8_H)
Reset Value: 0000X0X0_B
MSB
Bit No. CF_H
CE_H CD_H
CC_H
CB_H CA_H
LSB
C9_H C8_H
C8_H T2PS I3FR I2FR T2R
– T2CM –
T2I T2CON
The shaded bits are not used for interrupt control.
Bit
I2FR
I3FR
Function
External interrupt 2 rising/falling edge control flag
If I2FR = 0, the external interrupt 2 is activated by a falling edge at P5.4/INT2.
If I2FR = 1, the external interrupt 2 is activated by a rising edge at P5.4/INT2.
External interrupt 3 rising/falling edge control flag
If I3FR = 0, the external interrupt 3 is activated by a falling edge at P5.0/
T2CC0/INT3.
If I3FR = 1, the external interrupt 3 is activated by a rising edge at P5.0/
T2CC0/INT3.
The external interrupt 2 (INT2) can be either positive or negative transition-activated,
depending on bit I2FR in register T2CON. The flag that actually generates this interrupt
is bit IEX2 in register IRCON. The flag IEX2 is cleared by hardware when the service
routine is vectored to.
As with the external interrupt 2, the external interrupt 3 (INT3) can be either positive or
negative transition-activated, depending on bit I3FR in register T2CON. The flag that
actually generates this interrupt is bit IEX3 in register IRCON. In addition, this flag will be
set if a compare event occurs at pin P5.0/T2CC0/INT3, regardless of the compare mode
established and the transition at the respective pin. The flag IEX3 is cleared by hardware
when the service routine is vectored to.
The external interrupts 4 (INT4), 5(INT5) and 6(INT6) are positive transition-activated.
The flags that actually generate these interrupts are bits IEX4, IEX5 and IEX6 in register
IRCON. These flags will also be set if a compare event occurs at the corresponding Pins
P5.1/T2CC1/INT4, P5.2/T2CC2/INT5 and P5.3/T2CC3/INT6, regardless of the compare
mode established and the transition at the respective pin. When an interrupt is
generated, the flag that generated it is cleared by hardware when the service routine is
vectored to.
User’s Manual
7-13
2001-05