C508_01 Datasheet, PDF (23/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Fundamental Structure
Stack Pointer
The Stack Pointer (SP) Register is 8 bits wide. It is incremented before data is stored
during PUSH and CALL executions and decremented after data is popped during a POP
and RET (RETI) execution; that is, it always points to the last valid stack byte. While the
stack may reside anywhere in the on-chip RAM, the stack pointer is initialized to 07_H
after a reset. This causes the stack to begin at location = 08_H above register bank zero.
The SP can be read or written under software control.
2.2
CPU Timing
The C508 has no clock prescaler. Therefore, a machine cycle of the C508 consists of six
states (3 oscillator periods). Each state is divided into a Phase 1 half and a Phase 2 half.
Thus, a machine cycle consists of 3 oscillator periods, numbered S1P1 (State 1, Phase
1) through S6P2 (State 6, Phase 2). Each state lasts for half an oscillator period.
Typically, arithmetic and logic operations take place during Phase 1 and internal
register-to-register transfers take place during Phase 2.
The diagrams in Figure 2-2 show the fetch/execute timing related to the internal states
and phases. Since these internal clock signals are not user-accessible, the XTAL1
oscillator signals and the Address Latch Enable (ALE) signal are shown for external
reference. ALE is normally activated twice during each machine cycle: once during S1P2
and S2P1, and again during S4P2 and S5P1.
Execution of a one-cycle instruction begins at S1P2, when the op-code is latched into
the Instruction Register. If it is a two-byte instruction, the second reading takes place
during S4 of the same machine cycle. If it is a one-byte instruction, there is still a fetch
at S4, but the byte read (which would be the next op-code) is ignored (discarded fetch),
and the program counter is not incremented. In any case, execution is completed at the
end of S6P2.
Figure 2-2 (a) and (b) show the timings for a 1-byte, 1-cycle instruction and for a 2-byte,
1-cycle instruction.
Most C508 instructions are executed in one cycle. MUL (multiply) and DIV (divide) are
the only instructions that take more than two cycles to complete: they take four cycles.
Normally, two code bytes are fetched from the program memory during every machine
cycle. The only exception to this is when a MOVX instruction is executed. MOVX is a
one-byte, 2-cycle instruction that accesses external data memory. During a MOVX, the
two fetches in the second cycle are skipped while the external data memory is being
addressed and strobed. Figure 2-2 (c) and (d) show the timings for a normal 1-byte,
2-cycle instruction and for a MOVX instruction.
User’s Manual
2-5
2001-05