C508_01 Datasheet, PDF (221/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Interrupt System
7.3
Interrupt Priority Level Structure
The nineteen interrupt sources of the C508 are grouped according to the listing in
Table 7-1.
Table 7-1 Interrupt Source Structure
Interrupt
Group
Associated Interrupts
1
External
–
interrupt 0
A/D Converter
interrupt
2
Timer 0 overflow –
External
interrupt 2
3
External
CCU emergency External
interrupt 1
interrupt
interrupt 3
4
Timer 1 overflow Compare Timer 2 External
interrupt
interrupt 4
5
Serial channel Capture/Compare External
interrupt
match interrupt interrupt 5
6
Timer 2 overflow Compare Timer 1 External
interrupt
interrupt 6
–
–
External
interrupt 7
External
interrupt 8
External
interrupt 9
–
Each group of interrupt sources can be programmed individually to one of the four
priority levels by setting or clearing one bit in the Special Function Register IP0 and one
in IP1. A low-priority interrupt can be interrupted by a high-priority interrupt, but not by
another interrupt of the same or a lower priority. An interrupt of the highest priority level
cannot be interrupted by another interrupt source.
lf two or more requests of different priority levels are received simultaneously, the
request of the highest priority is serviced first. lf requests of the same priority level are
received simultaneously, an internal polling sequence determines which request is to be
serviced first. Thus, within each priority level there is a second priority structure
determined by the polling sequence. This is illustrated in Table 7-2.
User’s Manual
7-23
2001-05