C508_01 Datasheet, PDF (255/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
OTP Memory Operation
The following sections describe the details of the different access modes.
10.5
Program / Read OTP Memory Bytes
The program/read OTP memory byte access mode is defined by PMSEL1, 0 = 1, 1. It is
initiated when the PMSEL1, 0 = 1, 1 is valid at the rising edge of PALE. With the falling
edge of PALE, the upper addresses A8-A14 of the 15-bit OTP memory address are
latched. After A8-A14 has been latched, A0-A7 is put on the address bus (Port 2). A0-A7
must be stable when PROG is low or PRD is low. If subsequent OTP address locations
are accessed with constant address information at the high address lines A8-A14,
A8-A14 must only be latched once (page address mechanism).
Figure 10-5 shows a typical basic OTP memory programming cycle with a following
OTP memory read operation. In this example, A0-A14 of the read operation are identical
to A8-A14 of the proceeding programming operation.
PMSEL1, 0
Port 2
A8-
A14
PALE
Port 0
PROG
PRD
1, 1
A0-A7
D0-D7
min. 100 µs
D0-D7
min. 100 ns
MCT04094
Figure 10-5 Programming / Verify OTP Memory Access Waveform
If the address lines A8-A14 must be updated, PALE must be activated for the latching of
the new A8-A14 value. Control, address, and data information must only be switched
when the PROG and PRD signals are at high level. The PALE high pulse must always
be executed if a different access mode has been used prior to the actual access mode.
User’s Manual
10-9
2001-05