C508_01 Datasheet, PDF (128/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
On-Chip Peripheral Components
Compare Timer 1 Control Register
The 16-bit Compare Timer 1 is controlled by the bits of the CT1CON register. With this
register the count mode, the trap interrupt enable, the compare timer start/stop and
reset, and the timer input clock rate is controlled.
Special Function Register CT1CON (Address E1_H)
Reset Value: 00010000_B
Bit No. MSB
7
E1_H CTM
6
ETRP
5
4
3
STE1 CT1RES CT1R
2
CLK2
1
CLK1
LSB
0
CLK0
CT1CON
Bit
CTM
ETRP
STE1
CLK2
CLK1
CLK0
Function
Compare Timer 1 operating mode selection
CTM = 0 selects operating mode 0 (up count) and CTM = 1 selects operating
mode 1 (up/down count) for Compare Timer 1.
CCU emergency trap interrupt enable
If ETRP = 1, the emergency interrupt for the CCU trap signal is enabled.
CAPCOM unit shadow latch transfer enable
When STE1 is set, the content of the Compare Timer 1 period, Compare and
offset registers (CCPH, CCPL, CCHx, CCLx, CT1OFH, CT1OFL) is
transferred to its real registers when Compare Timer 1 reaches the next time
the period value or value 0000_H. After the shadow transfer event, STE1 is
reset by hardware.
Compare Timer 1 input clock selection
The input clock for the Compare Timer 1 is derived from the clock rate f_OSC
of the C508 via a programmable prescaler. The following table shows the
programmable prescaler ratios.
CLK2
0
0
0
0
1
1
1
1
CLK1
0
0
1
1
0
0
1
1
CLK0
0
1
0
1
0
1
0
1
Function
Compare timer 1 input clock is
Compare timer 1 input clock is
Compare timer 1 input clock is
Compare timer 1 input clock is
Compare timer 1 input clock is
Compare timer 1 input clock is
Compare timer 1 input clock is
Compare timer 1 input clock is
2 f_OSC
f_OSC
f_OSC/2
f_OSC/4
f_OSC/8
f_OSC/16
f_OSC/32
f_OSC/64
User’s Manual
6-63
2001-05