C508_01 Datasheet, PDF (232/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Fail Save Mechanisms
8.1.5 Watchdog Reset and Watchdog Status Flag
lf the software fails to refresh the Watchdog in time, an internally generated Watchdog
reset is entered at the counter state 7FFC_H. The duration of the reset signal then
depends on the prescaler selection (either 8 cycles or 128 cycles). This internal reset
differs from an external reset only in so far as the Watchdog Timer is not disabled and
bit WDTS (Watchdog Timer status, bit 6 in SFR IP0) is set. Figure 8-2 shows a block
diagram of all reset requests in the C508 and the function of the Watchdog Status flags.
The WDTS flag is a flip-flop which is set by a Watchdog Timer reset and cleared by an
external HW reset. Bit WDTS allows the software to examine from which source the
reset was activated. The Watchdog Timer Status flag can also be cleared by software.
OWD Reset Request
≥1
WDT Reset Request
Set Set
OWDS WDTS
IP0 (A9_H)
RESET
Clear
External HW Reset Request
Internal
Synchro- Reset
nization
Internal Bus
MCT04099
Figure 8-2 Watchdog Timer Status Flags and Reset Requests
User’s Manual
8-6
2001-05