C508_01 Datasheet, PDF (59/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

C508
Reset and System Clock Operation
5.2
Fast Internal Reset after Power-On
The C508 uses the Oscillator Watchdog unit for a fast internal reset procedure after
power-on. The clock source is provided by the RC Oscillator during the internal reset
procedure. When the on-chip oscillator is stabilized, its clock output is multiplied by a
fixed factor of two by the on-chip PLL. The clock from the PLL is then provided as the
system clock. Thus, the system clock frequency is twice the external oscillator
frequency. Figure 5-2 shows the power-on sequence under the control of the oscillator
watchdog.
Normally, devices in the 8051 family do not enter their default reset states before the on-
chip oscillator starts. This is because the external reset signal must be internally
synchronized and processed to bring the device into the correct reset state. The start up
time of the oscillator can be relatively long, especially if a crystal is used (typically 10 ms).
During this period, the pins have an undefined state which could have severe effects –
especially to actuators connected to port pins.
The Oscillator Watchdog unit in the C508 avoids this situation because its RC Oscillator
starts working within a very short startup time after power-on (typically less than 2 µs).
The on-chip oscillator that feeds the PLL has not started yet, and, thus, the PLL remains
unlocked. As long as the PLL is not locked, the watchdog uses the RC Oscillator output
as the clock source for the chip. This allows the part to be correctly reset and also brings
all ports to the defined state (see Figure 5-2, II). The exception is Port 1 which is used
as compare/capture outputs. These pins will be set to their default levels as soon as the
external reset is active. This is illustrated in Figure 5-3.
Under worst case conditions (fast V_DD rise time - such as 1 µs, measured from
V_DD = 4.25 V up to stable port condition), the delay between power-on and the correct
port reset state is:
– Typ.: 18 µs
– Max.: 34 µs
The RC oscillator will already run at a V_DD below 4.25 V (lower specification limit).
Therefore, at slower V_DD rise times, the delay time will be less than the two values given
above.
After the on-chip oscillator has started (Figure 5-2, III) and the PLL is locked, the
Oscillator Watchdog detects the correct function. Then, the watchdog continues to hold
the reset active for a time period of 768 cycles (maximum) of the RC oscillator clock to
ensure that a stable clock is available from the PLL (Figure 5-2, IV). Subsequently, the
system clock is supplied by the PLL and the oscillator watchdog’s reset is released
(Figure 5-2, V). However, an externally applied reset still remains active and the device
does not start program execution before the external reset is also released (Figure 5-2,
VI).
User’s Manual
5-3
2001-05