C508_01 Datasheet, PDF (191/267 Pages) Infineon Technologies AG – 8-Bit CMOS Microcontroller

Bit
ADCL1
ADCL0
C508
On-Chip Peripheral Components
Function
A/D Converter clock prescaler selection
ADCL1 and ADCL0 select the prescaler ratio for the A/D conversion
clock f_ADC. Depending on the clock rate f_OSC of the C508, f_ADC must
be adjusted in a way that the resulting conversion clock f_ADC is less
than or equal to 2 MHz (see Chapter 6.5.3).
The prescaler ratio is selected according to the following table:
ADCL1 ADCL0
0
0
0
1
1
0
1
1
Prescaler Ratio
divide by 4
divide by 8 (default after reset)
divide by 16
divide by 32
Note: Generally, before entering the power-down mode, an A/D conversion in progress
must be stopped. If a single A/D conversion is running, it must be terminated by
polling the BSY bit or waiting for the A/D conversion interrupt. In continuous
conversion mode, bit ADM must be cleared and the last A/D conversion must be
terminated before entering the power-down mode.
Note: Bit CLK of SFR ADCON0 must be written with a ‘0’.
A single A/D conversion is started by writing to SFR ADDATL with dummy data. A
continuous conversion is started under the following conditions:
– By setting bit ADM during a running single A/D conversion
– By setting bit ADM when at least one A/D conversion has occurred after the last
reset operation.
– By writing ADDATL with dummy data after bit ADM has been set (if no A/D
conversion has occurred after the last reset operation).
When bit ADM is reset by software in continuous conversion mode, the current A/D
conversion in progress will not be interrupted; it will be completed as the last conversion.
User’s Manual
6-126
2001-05