HD6433308 Datasheet, PDF (91/349 Pages) Hitachi Semiconductor – Hitachi Single-Chip MicroComputer

NMI and other edge-sensed interrupt request signals that arrive during the execution of an ANDC,
ORC, XORC, or LDC instruction are not lost. The request is latched in the interrupt controller and
detected after another instruction has been executed.
Program flow
LDC.B #H’00
← Interrupt request: ignored by interrupt controller
MOV.W #H’FF80,SP
← CPU executes next instruction: interrupt controller now
detects interrupt request
PUSH R1
← To interrupt-handling sequence
Figure 4-8. Example of Deferred Interrupt
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